1. Technical Field
Various embodiments may generally relate to a semiconductor integrated circuit device, and more particularly, to an input apparatus and a semiconductor memory apparatus having the input apparatus.
2. Related Art
In general, after semiconductor memory apparatuses are fabricated on a wafer, the chips may be tested through a wafer test process before the chips are individualized to determine whether or not there is a failure. The test process may also be performed at a packaging level after the chips fabricated on the wafer are individualized.
Because the test process is performed at the packaging level, the test process at the wafer level may tend to be simplified, and thus only the minimum number of pins may be used in the wafer test process.
Due to a reduction in the number of test pins at the wafer test, fabrication costs associated with a probe card may be saved and a test parameter may be reduced.
An address, data, and the like required for the test operation may have to be input within a preset time. For example, n/m input pins may be necessary to input n signals for m clock cycles.
When more signals are input using less input pins within a preset clock cycle, the pin reduction efficiency can be expected to increase at the wafer test performed within the pin reduction mode.